The present invention relates to a method of designing a mask pattern to be formed in a mask for use with a lithography process and a method of manufacturing an integrated circuit through the mask produced on the basis of said method of designing a mask pattern.
Generally, an integrated circuit is designed according to a method of combining partial circuits having a size easy to handle, and each partial circuit is called "circuit block". A pattern constituting an integrated circuit generally belongs to one of circuit blocks. In a conventional method of designing a mask pattern to be formed in a mask used with a lithography process, the circuit blocks which are designed in advance are automatically arranged so as to attain a minimum chip area. In the automatic arrangement of the circuit blocks, there is employed an algorithm in which the distances between the circuit blocks are decreased so as to be smallest possible. Meanwhile, the circuit blocks having a larger number of patterns and the circuit blocks having a smaller number of patterns exist in one chip. When the chip is divided into meshes having the form of a lattice and pattern area ratios .alpha.' of the meshes are determined, the pattern area ratios .alpha.' greatly vary.
In one of the techniques for coping with an increase in the integration degree of integrated circuits, flattening treatment is carried out when an integrated circuit is produced. A chemical/mechanical polishing process (to be sometimes simply referred to as "CMP" hereinafter) is among techniques for the flattening treatment. FIG. 11 schematically shows a polishing apparatus for use with the above CMP process. The polishing apparatus has a polishing plate, a substrate holder and an abrasive slurry feeding system. The polishing plate is supported with a rotatable polishing plate rotation shaft, and is provided with a polishing pad on its surface. The substrate holder is disposed above the polishing plate and supported with a substrate hold rotation shaft. For example, when a substrate is polished, the substrate is attached to the substrate holder. The substrate holder rotation shaft is attached to a polishing pressure adjusting mechanism (not shown) which thrusts the substrate holder toward the polishing pad. Then, while an abrasive slurry containing an abrasive is fed to the polishing pad from the abrasive slurry feeding system, the polishing plate is turned. At the same time, the substrate attached to the substrate holder is turned, and the pressure between the substrate and the polishing pad is adjusted with the polishing pressure adjusting mechanism. In this manner, the surface of the substrate is polished.
The outline of a conventional CMP process will be explained with reference to FIGS. 17A to 17D below. As shown in the schematic partial cross-sectional view of FIG. 17A, first, a first layer 11 composed of, for example, polysilicon doped with an impurity is deposited on an underlayer 10 composed of, for example, an insulation layer. Then, a pattern is formed in the first layer 11 by lithography and etching (see FIG. 17B). A patterned portion of the first layer is indicated by reference numeral 12. Then, a second layer 14 (for example, an insulation layer) is deposited on the entire surface (see FIG. 17C), and the second layer 14 is flattened by the CMP process. However, when the pattern area ratios .alpha.' greatly vary in the patterned first layer 12, the following problem takes place. That is, a portion of the second layer 14 on a portion of the first layer 12 having a lower pattern area ratio .alpha.' is much more polished than a portion of the second layer 14 on a portion of the first layer 12 having a higher pattern area ratio .alpha.' (see FIG. 17D). This phenomenon is called "dishing". As a result, the flattening treatment of the second layer 14 is made difficult.
One method of overcoming the above problem is disclosed in Extended Abstract of the 1996 International Conference on Solid State Device and Materials, S. Deleonibus, et al., YOKOHAMA, pp. 836-838. As shown in schematic partial cross-sectional views of FIGS. 18A and 18B, it is assumed that an area of the first layer 12 having a high pattern area ratio .alpha.' and an area of the first layer 12 having a low pattern area ratio .alpha.' are included, and the area of the first layer 12 having a high pattern area ratio .alpha.' is schematically shown as a rectangular form. In the above method, a resist 40 is formed on the second layer 14 (see FIG. 18C). The resist 40 is then patterned by lithography such that the second layer 14 on the area of the first layer 12 having a high pattern area ratio .alpha.' is not covered with the resist 40 (see FIG. 19A). Then, the patterned resist 40 is used to partially etch the second layer 14 in a thickness direction (see FIG. 19B). Thereafter, the resist 40 is removed, and the CMP process is applied to the remaining layer 14.
In the above manner, the second layer 14 can be flattened regardless of the pattern area ratios .alpha.' of the patterned first layer 12. However, the above method has the following problems. The step of patterning the resist 40 and the step of etching the second layer 14 are required, so that the number of steps of the CMP process as a whole increases. Moreover, it is difficult to control the depth when the second layer 14 is partially etched in a depth direction. Further, there is another problem that the manufacturing cost of integrated circuits increases, and the yield thereof decreases.